Japanese Patent Application No. 2005-262389 filed on Sep. 9, 2005, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to an integrated circuit device and an electronic device.
2. Related Art
As an integrated circuit device driving a display panel such as a liquid crystal panel, there is known as a display driver (LCD driver). For this display driver, it is required to reduce chip size in order to achieve reduction in cost.
However, the display panels mounted into, for example, cell-phones have a substantially constant size. Therefore, when a fine designing process is employed and the integrated circuit device of the display driver is merely shrinked to thereby reduce a chip size, there arises a problem in that mounting it on a panel may become difficult.
Further, when the user mounts the display drivers into the liquid crystal panels to thereby manufacture the display devices, various adjustments are necessary at the display driver side. In other words, it is necessary to perform adjustments so as to accommodate the display drivers to the specifications of the panels (for example, an amorphous TFT, a low-temperature poly-silicon TFT, a QCIF, a QVGA, and a VGA) or the specifications of driving conditions. Furthermore, it is necessary to perform adjustment so as to prevent variation in display properties among the panels. Also at the IC manufacturer side, the adjustment of the oscillating frequency or of output voltage, the switching to a redundant memory or the like is needed during the IC test.
Conventionally, the adjustments at the user side have been performed by an external Electrical Erasable Programmable Read Only Memory (E2PROM) or an external trimmer resistance (variable resistance). The switching to the redundant memory or the like at the IC manufacturer side has been performed by blowing out a fuse element provided inside the integrated circuit device.
However, the mounting work of the components is complicated for the user. Moreover, there is a disadvantage in that the trimmer resistance is expensive, large, and apt to be broken. Also at the IC manufacturer side, the blowing out of the fuse element and the work for operation test thereafter are complicated.
In view of the above, JP-A-S63-166274 has been proposed a nonvolatile memory device which can be manufactured in easier manufacturing process and at a lower cost as compared to a stack gate type nonvolatile memory device having two gates. In the nonvolatile memory device according to JP-A-63-166274, a control gate is an N type impurity region inside a semiconductor layer, and a floating gate electrode is composed of a conductive layer such as a single layer poly-silicon (hereinafter, the nonvolatile memory device according to JP-A-63-166274 is also referred to as a “single layer gate type nonvolatile memory device”). Such the single layer gate type nonvolatile memory device does not require the gate electrodes stacked, so it can be formed in a process for a normal CMOS transistor.
JP-A-2001-222249 is an example of related art.